Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis

This paper considers the problem of partitioning analog integrated circuits for hierarchical symbolic analysis based on determinant decision diagrams (DDDs). The objective is to use DDDs with the minimum number of vertices to represent all the symbolic expressions. We show that the problem can be formulated as that of multi-level multi-way hyper graph partitioning with balance constraints, and be solved in two phases by connectivity-oriented initial clustering and iterative improvement. Our new contribution consists of a fast and effective heuristic for constructing a balanced initial partition, a potential gain formulae that can be computed efficiently, and a multiple-vertex moving strategy for relaxing and enforcing balance constraints. The proposed algorithm has been implemented and applied to symbolic analysis of several practical analog integrated circuits. Experimental results are described and compared to the contour tableau method of Sangiovanni-Vincentelli, Chen and Chua, and the SCAPP algorithm of Hassoun and Lin. The resulting hierarchical symbolic analyzer outperforms SPICE in numerical evaluations for a number of large analog circuits. r 2003 Elsevier Science B.V. All rights reserved.